芯片設(shè)計(jì)EDA工具培訓(xùn)合集
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培訓(xùn)方向 |
具體課程 |
課時 |
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數(shù)字IC驗(yàn)證 |
SystemVerilog Assertions |
3 days |
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SystemVerilog Testbench |
3 days |
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SystemVerilog UVM |
3 days |
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數(shù)字IC后端 |
Design Compiler NXT RTL Synthesis |
3 days |
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Synopsys PrimeTime |
3 days |
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Synopsys ICCII Block Lever Implementation |
3 days |
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Synopsys ICCII SoC Design Planning |
2 days |
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Formality |
2 days |
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Mentor calibre LVS DRC |
3 days |
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Synopsys startRC |
2 days |
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Mentor Calibre Perc+dfm |
2 days |
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Synopsys PrimeTime |
1 days |
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可測試性 |
Synopsys DFT Compiler |
3 days |
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Synopsys TetraMax |
3 days |
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Mentor Tessent ATPG + MBIST |
5 days |
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功耗分析與低功耗 |
Synopsys Low Power Flow HLD (Front-End) |
2 days |
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Synopsys Low Power Flow P&R (Backend Flow) |
1 days |
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Synopsys PrimeTime PX: Signoff Power Analysis |
1 days |
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Power-Aware Verification with VCS-NLP and UPF |
1 days |
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模擬IC設(shè)計(jì)與仿真 |
Synopsys Hspice Advanced Topics |
2 days |
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Mentor AFS |
2 days |
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Mentor Tanner |
3 days |
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